REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE
Researchers from UC Berkeley and the Lawrence Berkeley National Lab are engaged in a
co-operative effort for ?application-driven hardware design? that engages application scientists in the early parts of the hardware design process for future generation supercomputing systems. These partnerships foster development of computing systems that are better tuned to the application requirements of demanding scientific applications and result in more cost-effective and efficient HPC system designs. However, it can take years for each new iteration of hardware to become available for testing and evaluation by the application scientists. The current plodding pace of this feedback loop thus dramatically limits the pace of progress. Therefore, we are using the Berkeley RAMP system (Research Accelerator for Multiple Processors) as a hardware emulation environment to facilitate and ultimately accelerate the iterative process of science-driven system design.
Our goal is to develop and demonstrate a design methodology for domain-optimized computer
system architectures. We plan to develop a methodology and tools for rapid prototyping and design-
space exploration. Although the techniques we will demonstrate have broad applicability, such as in
the design of energy-efficient datacenters or even embedded applications, HPC is our primary area
of interest.
Choose a quarter and click "Go."
| AWARD OVERVIEW |
| Award Number |
DE-SC0003624 |
Funding Agency |
Department of Energy |
| Total Award Amount |
$2,670,000 |
Project Location - City |
Berkeley |
| Award Date |
08/06/2012 |
Project Location - State |
CA |
| Project Status |
More than 50% Completed |
Project Location - Zip |
94720-1500
|
| Jobs Reported |
1.26 |
Congressional District |
13 |
| Project Location - Country |
US |
|
|
Recipient Information
(Grants)
| Recipient Information (Grants) |
|
Recipient Name
|
REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE |
| Recipient DUNS Number |
124726725
|
| Recipient Address |
2150 SHATTUCK AVE RM 313 |
| Recipient City |
BERKELEY |
| Recipient State |
California |
| Recipient Zip |
94704-5940 |
| Recipient Congressional District |
13 |
| Recipient Country |
USA |
Required to Report Top 5
Highly Compensated Officials |
No |
Projects and Jobs Information
| Projects and Jobs Information |
| Project Title |
TAS::89 0227::TAS Recovery Act - Accelerating Science Driven System Design with RAMP |
| Project Status |
More than 50% Completed |
| Final Project Report Submitted |
No |
| Project Activities Description |
Universities |
| Quarterly Activities/Project Description |
Chisel hardware construction language is now in production status with a stable server, a regularly-exercised design flow, and a discipline of nightly builds. Adoption by external DOE computer architecture efforts is underway with collaborators at LBL and Sandia, among others.
Packaging of the Raven series of RISC V processors is being performed at ST Micro on a ceramic substrate for 17x17 fBGA, and a fine-line organic board flip chip board under exploration. FIB was unsuccessful for F1 but corrected B1 to functional silicon. Planning is continuing for POP-mounted LPDDR2 for the next build (validated commercial host-attached memory).
A rocket core for the Horus chiplet is being prepared for ASIC synthesis, and is closely matched with the FPGA simulated version. The ultimate target for this silicon is the silicon circuit board described earlier and below. The IO chip completed automated tool flow required for parameterization during this quarter targeting a TSMC 65nm LP library.
The silicon circuit board for the chiplet effort has made significant progress; at this point the design is essentially complete for both versions 1 and 2. For initial production, several nano-pulse laser manufacturers were evaluated, and testing of a switching laser is required to minimize debris thus providing a clean patterning of the metal and dielectric has been successfully completed. The second test run (March 2013) yielded showed excellent ablation results with 20 micron pitch (12 micron wide ablation track and 8 micron copper). Our preferred service bureau Mounds was able to greatly speed the process (and lower cost) and multiple test wafers have been processed with PCB dielectric. Multiple layering is now being performed in NC, and the overall process indicates great promise for low-cost one-off prototyping at micron scale. We are investigating Hybrid Memory Cube as an alternative memory solution and initiated discussions with developers at Micron and IBM. |
| Jobs Created |
1.26 |
| Description of Jobs Created |
Jobs Created and Jobs Retained: ARRA funds were used to support 0.757 FTE retained graduate student researchers to develop RTL components and perform analysis on proposed architectures, support 0.30 FTE retained engineering positions for system design activities and software support, and provide 0.20 FTE retained computer systems and technical academic support personnel. |
Purchaser Information
(Grants)
| Purchaser Information |
| Contracting Office ID |
Not Reported |
| Contracting Office Name |
Not Available |
| Contracting Office Region |
Not Available |
| TAS Major Program |
89-0331 |
| Award Information |
| Award Date |
08/06/2012 |
| Award Number |
DE-SC0003624 |
| Order Number |
|
| Award Type |
Grants |
| Funding Agency ID |
89 |
| Funding Agency Name |
Department of Energy |
| Funding Office Name |
Not Available |
| Awarding Agency ID |
89 |
| Awarding Agency Name |
Department of Energy |
| Amount of Award |
$2,670,000 |
| Funds Invoiced/Received |
$2,391,266 |
| Expenditure Amount |
$2,389,542 |
| Infrastructure Expenditure Amount |
$0 |
| Infrastructure Purpose and Rationale |
Not Reported |
| Infrastructure Point of Contact Name |
Not Reported |
| Infrastructure Point of Contact Email |
Not Reported |
| Infrastructure Point of Contact Phone |
Not Reported |
| Infrastructure Point of Contact Address |
Not Reported |
| Infrastructure Point of Contact City |
Not Reported |
| Infrastructure Point of Contact State |
Not Reported |
| Infrastructure Point of Contact Zip |
Not Reported |
Product or Service Information
(Grants)
| Product or Service Information |
| Primary Activity Code |
B43 - NTEE |
| Activity Description |
Universities |
| Sub-Awards Information |
| Sub-awards to Organizations |
0 |
| Sub-award Amounts to Organizations |
$0 |
| Sub-Awards to Individuals |
0 |
| Sub-Award Amounts to Individuals |
$0 |
| Number of Sub-awards less than $25,000/award |
0 |
| Amount of Sub-awards less than $25,000/award |
$0 |
| Number of payments to vendors greater than $25,000 |
2 |
| Total Amount of payments to vendors greater than $25,000/award |
$98,575 |
| Number of payments to vendors less than $25,000/award |
111 |
| Total Amount of payments to vendors less than $25,000/award |
$211,731 |
Beecube Inc - Award Number DE-SC0003624 - Beecube Inc
| Award Number |
DE-SC0003624 |
| Sub-Award Number |
N/A |
| Vendor DUNS Number |
801214433 |
| Vendor HQ Zip Code + 4 |
94506 |
| Vendor Name |
Beecube Inc |
| Product and Service Description |
BEE4 LX550T-U Base Configuration for universities; 4DDR3-1066 Memory (4GB RDIMMs/BEE4-16GB-U); warranty. Used to test hardware on a FPGA emulation platform. |
| Payment Amount |
$49,188 |
Beecube Inc - Award Number DE-SC0003624 - Beecube Inc
| Award Number |
DE-SC0003624 |
| Sub-Award Number |
N/A |
| Vendor DUNS Number |
801214433 |
| Vendor HQ Zip Code + 4 |
94506 |
| Vendor Name |
Beecube Inc |
| Product and Service Description |
BEE4 LX240T Base Configuration for universities; 4DDR3-1066 Memory (4GB RDIMMs/BEE4-16GB-U); warranty. Used to test hardware on a FPGA emulation platform. |
| Payment Amount |
$49,388 |
| Location Information |
| Latitude, Longitude |
37º 52' 17",
-122º 15' 37" |
| Congressional District |
13 |
| Address 1 |
|
| Address 2 |
|
| City |
Berkeley |
| County |
Alameda |
| State |
CA |
| Zip |
94720-1500 |
|
 |